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Oscillator Frequency Upconverter AD9552
FEATURES
Converts a low frequency input reference signal to a high frequency output signal Input frequencies from 6.6 MHz to 112.5 MHz Output frequencies up to 900 MHz Preset pin programmable frequency translation ratios Arbitrary frequency translation ratios via SPI port On-chip VCO Accepts a crystal resonator and/or an external oscillator as a reference frequency source Secondary output (either integer-related to the primary output or a copy of the reference input) RMS jitter: <0.5 ps SPI-compatible, 3-wire programming interface Single supply (3.3 V) Very low power: <400 mW (under most conditions) Small package size (5 mm x 5 mm)
GENERAL DESCRIPTION
The AD9552 is a fractional-N phase locked loop (PLL) based clock generator designed specifically to replace high frequency crystal oscillators and resonators. The device employs a sigmadelta (-) modulator (SDM) to accommodate fractional frequency synthesis. The user supplies an input reference signal by connecting a single-ended clock signal directly to the REF pin or by connecting a crystal resonator across the XTAL pins. The AD9552 is pin programmable, providing one of 64 standard output frequencies based on one of eight common input frequencies. The device also has a 3-wire SPI interface, enabling the user to program custom input-to-output frequency ratios. The AD9552 relies on an external capacitor to complete the loop filter of the PLL. The output is compatible with LVPECL, LVDS, or single-ended CMOS logic levels, although the AD9552 is implemented in a strictly CMOS process. The AD9552 is specified to operate over the extended industrial temperature range of -40C to +85C.
APPLICATIONS
Cost effective replacement of high frequency VCXO, OCXO, and SAW resonators Extremely flexible frequency translation with low jitter for SONET/SDH (including FEC), 10 Gb Ethernet, Fibre Channel, and DRFI/DOCSIS High-definition video frequency translation Wireless infrastructure Test and measurement (including handheld devices)
BASIC BLOCK DIAGRAM
AD9552
REF XTAL INPUT FREQUENCY SOURCE SELECTOR OUT2 PLL OUTPUT CIRCUITRY OUT1
PIN-DEFINED AND SERIAL PROGRAMMING
07806-001
Figure 1.
Rev. C
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AD9552 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Basic Block Diagram ........................................................................ 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Crystal Input Characteristics ...................................................... 4 Output Characteristics ................................................................. 4 Jitter Characteristics ..................................................................... 5 Serial Control Port ....................................................................... 6 Serial Control Port Timing ......................................................... 6 Absolute Maximum Ratings............................................................ 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Typical Performance Characteristics ............................................. 9 Input/Output Termination Recommendations .......................... 12 Theory of Operation ...................................................................... 13 Preset Frequency Ratios ............................................................ 13 Component Blocks ..................................................................... 15 Part Initialization and Automatic Power-On Reset ............... 17 Output/Input Frequency Relationship .................................... 17 Calculating Divider Values ....................................................... 17 Low Dropout (LDO) Regulators .............................................. 18 Applications Information .............................................................. 19 Thermal Performance ................................................................ 19 Serial Control Port ......................................................................... 20 Serial Control Port Pin Descriptions ....................................... 20 Operation of the Serial Control Port ....................................... 20 Instruction Word (16 Bits) ........................................................ 21 MSB/LSB First Transfers ........................................................... 21 Register Map ................................................................................... 23 Register Map Descriptions ........................................................ 24 Outline Dimensions ....................................................................... 30 Ordering Guide .......................................................................... 30
REVISION HISTORY
7/10--Rev. B to Rev. C Changed Crystal Load Capacitance to 15 pF............. Throughout Added Conditions Statement to Specifications Section, Supply Voltage Specifications, and Input Voltage Specifications ............ 3 Reformatted Specifications Section (Renumbered Sequentially)..... 3 Added Input/Output Termination Recommendations Section, Figure 17, and Figure 18 (Renumbered Sequentially) ............... 13 Moved Preset Frequency Ratios Section ..................................... 13 Changes to Component Blocks Section ...................................... 15 Added Part Initialization and Automatic Power-On Reset Section ................................................................................... 17 4/10--Rev. A to Rev. B Changes to Preset Frequency Ratios Section .............................. 12 Moved Table 15 and Changes to Table 15 ................................... 13 Changes to Figure 17 ...................................................................... 14 Changes to PLL Section, Output Dividers Section, and Input-to-OUT2 Option Section ............................................... 15 Changes to Output/Input Frequency Relationship Section ...... 16 Changes to Table 22 ....................................................................... 23 Changes to Table 26 ....................................................................... 26 9/09--Rev. 0 to Rev. A Changes to Table 4.............................................................................3 Changes to Table 5.............................................................................4 Added Table 6; Renumbered Sequentially .....................................4 Changes to Figure 5 ...........................................................................9 Changes to PLL Section ................................................................. 14 Changes to Table 22 ....................................................................... 21 Changes to Table 25 ....................................................................... 24 7/09--Revision 0: Initial Version
Rev. C | Page 2 of 32
AD9552 SPECIFICATIONS
Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ) values apply for VDD = 3.3 V; TA = 25C, unless otherwise noted. Table 1.
Parameter SUPPLY VOLTAGE POWER CONSUMPTION Total Current VDD Current By Pin Pin 7 Pin 18 Pin 21 Pin 28 LVPECL Output Driver LOGIC INPUT PINS INPUT CHARACTERISTICS 1 Logic 1 Voltage, VIH Logic 0 Voltage, VIL Logic 1 Current, IIH Logic 0 Current, IIL LOGIC OUTPUT PINS Output Characteristics Output Voltage High, VOH Output Voltage Low, VOL RESET PIN Input Characteristics 2 Input Voltage High, VIH Input Voltage Low, VIL Input Current High, IINH Input Current Low, IINL Minimum Pulse Width High REFERENCE CLOCK INPUT CHARACTERISTICS Frequency Range Min 3.135 Typ 3.30 149 2 77 35 35 36 Max 3.465 169 3 86 41 41 41 Unit V mA mA mA mA mA mA Test Conditions/Comments Pin 7, Pin 18, Pin 21, Pin 28 At maximum output frequency with both output channels active
900 MHz with 100 termination between both pins of the output driver
1.0 0.8 3 17
V V A A
For the CMOS inputs, a static Logic 1 results from either a pull-up resistor or no connection
2.7 0.4
V V
1.8 0.3 31 2 1.3 12.5 43
V V A A ns
7.94 6.57
MHz MHz
93.06 71.28 112.5
MHz MHz MHz
86.17
MHz
N3 = 255; 2x frequency multiplier enabled; valid for all VCO bands N 3 = 255; 2x frequency multiplier enabled; fVCO = 3.35 GHz, which constrains the frequency at OUT1 to be an integer sub-multiple of 3.35 GHz (that is, fOUT1 = 3.35 / M GHz, where M is the product of the P0 and P1 output divider values) SDM4 disabled; N3 = 365; valid for all VCO bands SDM4 enabled; N3 = 476; valid for all VCO bands SDM 4 disabled; N3 = 36 5 ; fVCO = 4.05 GHz, which constrains the frequency at OUT1 to be an integer sub-multiple of 4.05 GHz (that is, fOUT1 = 4.05/M GHz, where M is the product of the P0 and P1 output divider values) SDM4 enabled; N3 = 47 6 ; fVCO = 4.05 GHz, which constrains the frequency at OUT1 to be an integer sub-multiple of 4.05 GHz (that is, fOUT1 = 4.05/M GHz, where M is the product of the P0 and P1 output divider values)
Rev. C | Page 3 of 32
AD9552
Parameter Input Capacitance Input Resistance Duty Cycle Input Voltage Input High Voltage, VIH Input Low Voltage, VIL Input Threshold Voltage VCO CHARACTERISTICS Frequency Range Upper Bound Lower Bound VCO Gain VCO Tracking Range VCO Calibration Time 300 140 Min Typ 3 130 Max Unit pF k % V V V Test Conditions/Comments
40 0.52
60
1.62 1.0
When ac coupling to the input receiver, the user must dc bias the input to 1 V
4050 3350 45
MHz MHz MHz/V ppm s fPFD 7 = 77.76 MHz; time between completion of the VCO calibration command (the rising edge of CS (Pin 12)) to the rising edge of LOCKED (Pin 20).
1 2 3
The A[2:0], Y[5:0], and OUTSEL pins have 100 k internal pull-up resistors. The RESET pin has a 100 k internal pull-up resistor, so the default state of the device is reset. N is the integer part of the feedback divider. 4 Sigma-delta modulator. 5 The minimum allowable feedback divider value with the SDM disabled. 6 The minimum allowable feedback divider value with the SDM enabled. 7 The frequency at the input to the phase-frequency detector.
CRYSTAL INPUT CHARACTERISTICS
Table 2.
Parameter CRYSTAL FREQUENCY Range Tolerance CRYSTAL MOTIONAL RESISTANCE CRYSTAL LOAD CAPACITANCE Min 10 Typ 26 Max 52 20 100 Unit MHz ppm pF Test Conditions/Comments
15
Using a crystal with a specified load capacitance other than 15 pF (8 pF to 24 pF) is possible, but necessitates using the SPI port to configure the AD9552 crystal input capacitance.
OUTPUT CHARACTERISTICS
Table 3.
Parameter LVPECL MODE Differential Output Voltage Swing Common-Mode Output Voltage Frequency Range Duty Cycle Rise/Fall Time 1 (20% to 80%) Min 690 VDD - 1.77 0 40 Typ 765 VDD - 1.66 Max 889 VDD - 1.20 900 60 305 Unit mV V MHz % ps Test Conditions/Comments Output driver static Output driver static Up to 805 MHz output frequency 100 termination between both pins of the output driver
255
Rev. C | Page 4 of 32
AD9552
Parameter LVDS MODE Differential Output Voltage Swing Balanced, VOD Unbalanced, VOD Min Typ Max Unit Test Conditions/Comments
247
454 25
mV mV
Voltage swing between output pins; output driver static Absolute difference between voltage swing of normal pin and inverted pin; output driver static Output driver static Voltage difference between output pins; output driver static
Offset Voltage Common Mode, VOS Common-Mode Difference, VOS Short-Circuit Output Current Frequency Range Duty Cycle Rise/Fall Time1 (20% to 80%) CMOS MODE Output Voltage High, VOH IOH = 10 mA IOH = 1 mA Output Voltage Low, VOL IOL = 10 mA IOL = 1 mA Frequency Range Duty Cycle Rise/Fall Time1 (20% to 80%)
1
1.125
1.375 25 17 24 900 60 355
V mV mA MHz % ps
0 40 285
Up to 805 MHz output frequency 100 termination between both pins of the output driver Output driver static; standard drive strength setting
2.8 2.8
V V Output driver static; standard drive strength setting 0.5 0.3 200 55 745 V V MHz % ps
0 45 500
3.3 V CMOS; standard drive strength setting At maximum output frequency 3.3 V CMOS; standard drive strength setting; 15 pF load
The listed values are for the slower edge (rise or fall).
JITTER CHARACTERISTICS
Table 4.
Parameter JITTER GENERATION 12 kHz to 20 MHz 50 kHz to 80 MHz 4 MHz to 80 MHz JITTER TRANSFER BANDWIDTH JITTER TRANSFER PEAKING Min Typ 0.64 0.70 0.47 0.50 0.11 0.12 100 0.3 Max Unit ps rms ps rms ps rms ps rms ps rms ps rms kHz dB Test Conditions/Comments Input = 19.44 MHz crystal resonator fOUT = 622.08 MHz (integer mode) fOUT = 625 MHz (fractional mode) fOUT = 622.08 MHz (integer mode) fOUT = 625 MHz (fractional mode) fOUT = 622.08 MHz (integer mode) fOUT = 625 MHz (fractional mode) See the Typical Performance Characteristics section See the Typical Performance Characteristics section
Rev. C | Page 5 of 32
AD9552
SERIAL CONTROL PORT
Table 5.
Parameter CS Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SCLK Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO Input Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance Output Output Logic 1 Voltage Output Logic 0 Voltage Min 1.6 0.5 0.03 2 2 1.6 0.5 2 0.03 2 Typ Max Unit V V A A pF V V A A pF Test Conditions/Comments
1.6 0.5 1 1 2 2.8 0.3
V V A A pF V V 1 mA load current 1 mA load current
SERIAL CONTROL PORT TIMING
Table 6.
Parameter SCLK Clock Rate, 1/tCLK Pulse Width High, tHIGH Pulse Width Low, tLOW SDIO to SCLK Setup, tDS SCLK to SDIO Hold, tDH SCLK to Valid SDIO, tDV CS to SCLK Setup (tS) and Hold (tH) CS Minimum Pulse Width High Limit 50 3 3 4 0 13 0 6.4 Unit MHz max ns min ns min ns min ns min ns max ns min ns min
Rev. C | Page 6 of 32
AD9552 ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Supply Voltage (VDD) Maximum Digital Input Voltage Storage Temperature Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Rating 3.6 V -0.5 V to VDD + 0.5 V -65C to +150C -40C to +85C 300C 150C
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. C | Page 7 of 32
AD9552 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32 31 30 29 28 27 26 25 Y3 Y2 Y1 Y0 VDD OUT1 OUT1 GND
Y4 Y5 A0 A1 A2 RESET VDD LDO
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
AD9552
TOP VIEW (Not to Scale)
24 23 22 21 20 19 18 17
GND OUT2 OUT2 VDD LOCKED LDO VDD LDO
XTAL XTAL REF CS SCLK SDIO OUTSEL FILTER
9 10 11 12 13 14 15 16
NOTES 1. EXPOSED DIE PAD MUST BE CONNECTED TO GND.
Figure 2. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. 29, 30, 31, 32, 1, 2 3, 4, 5 6 7, 18, 21, 28 8, 17, 19 9, 10 11 12 13 14 15 Mnemonic Y0, Y1, Y2, Y3, Y4, Y5 A0, A1, A2 RESET VDD LDO XTAL REF CS SCLK SDIO OUTSEL Type1 I Description Control Pins. These pins select preset values for the PLL feedback divider and the OUT1 dividers based on the input reference frequency selected via the A[0:2] pins and have internal 100 k pull-up resistors. Control Pins. These pins select the input reference frequency and have internal 100 k pullup resistors. Digital Input, Active High. Resets internal logic to default states. This pin has an internal 100 k pull-up resistor, so the default state of the device is reset. Power Supply Connection: 3.3 V Analog Supply. LDO Decoupling Pins. Connect a 0.47 F decoupling capacitor from each of these pins to ground. Crystal Resonator Input. Connect a crystal resonator across these pins. Reference Clock Input. Connect this pin to an active clock input signal, or connect it to VDD when using a crystal resonator across the XTAL pins. Digital Input, Active Low, Chip Select. Serial Data Clock. Digital Serial Data Input/Output. Logic 0 selects LVDS and Logic 1 selects LVPECL-compatible levels for both OUT1 and OUT2 when the outputs are not under SPI port control. Can be overridden via the programming registers. This pin has an internal 100 k pull-up resistor. Loop Filter Node for the PLL. Connect an external 12 nF capacitor from this pin to Pin 17 (LDO). Active High Locked Status Indicator for the PLL. Complementary Square Wave Clocking Outputs. Square Wave Clocking Outputs. Analog Ground. The exposed die pad must be connected to GND.
I I P P/O I I I I I/O I
16 20 26, 22 27, 23 24, 25 EP
1
FILTER LOCKED OUT1, OUT2 OUT1, OUT2 GND Exposed Die Pad
I/O O O O P
I = input, I/O = input/output, O = output, P = power, P/O = power/output.
Rev. C | Page 8 of 32
07806-002
AD9552 TYPICAL PERFORMANCE CHARACTERISTICS
-20 -30 -40 -50
PHASE NOISE (dB)
CARRIER 624.988784MHz
0.4009dBm
-20 -30 -40 -50
PHASE NOISE (dB)
CARRIER 622.068199MHz
0.5831dBm
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 100
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 100
07806-014
1k
10k 100k 1M FREQUENCY (Hz)
10M
100M
1k
10k 100k 1M FREQUENCY (Hz)
10M
100M
Figure 3. Phase Noise, Fractional-N, Pin Programmed (fXTAL = 19.44 MHz, fOUT1 = 625 MHz)
CARRIER 624.999995MHz 0.4057dBm
Figure 6. Phase Noise, Integer, SDM Off (fXTAL = 19.44 MHz, fOUT1 = 622.08 MHz)
CARRIER 622.079986MHz 0.3798dBm
-20 -30 -40 -50
PHASE NOISE (dB)
-20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 100
-80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 100
07806-015
PHASE NOISE (dB)
-60 -70
1k
10k 100k 1M FREQUENCY (Hz)
10M
100M
1k
10k 100k 1M FREQUENCY (Hz)
10M
100M
Figure 4. Phase Noise, Fractional-N, Pin Programmed (fREF = 19.44 MHz, fOUT1 = 625 MHz)
10 0 JITTER TRANSFER
JITTER TRANSFER (dB)
SUPPLY CURRENT (mA) 35
Figure 7. Phase Noise, Integer, SDM Off (fREF = 19.44 MHz, fOUT1 = 622.08 MHz)
30
LVPECL
-10 -20
1 0
25
JITTER PEAKING
20 LVDS (STRONG) 15
-30
-1
-40
-2
-50
10
-3 1k 10k 100k
07806-018
LVDS (WEAK)
10k
100k 1M FREQUENCY OFFSET (Hz)
10M
1k FREQUENCY (MHz)
Figure 5. Jitter Transfer and Jitter Peaking
Figure 8. Supply Current vs. Output Frequency, LVPECL and LVDS (15 pF Load)
Rev. C | Page 9 of 32
07806-019
-60 1k
5 100
07806-017
07806-016
AD9552
25
1.6 LVPECL
1.4
20
SUPPLY CURRENT (mA)
AMPLITUDE (V p-p)
1.2 LVDS (STRONG) 1.0
15
10
0.8 LVDS (WEAK) 0.6
5
07806-020
0
50
100 150 FREQUENCY (MHz)
200
250
0
200
400 600 FREQUENCY (MHz)
800
1000
Figure 9. Supply Current vs. Output Frequency, CMOS (15 pF Load)
4.0 3.5 3.0 60
Figure 12. Peak-to-Peak Output Voltage vs. Frequency, LVPECL and LVDS (15 pF Load)
5pF
AMPLITUDE (V p-p)
2.5
20pF
2.0 1.5 1.0 0.5
07806-021
DUTY CYCLE (%)
10pF
55
LVDS (WEAK) LVDS (STRONG) LVPECL 0 100 200 300 FREQUENCY (MHz) 400 500 200 300 400 500 600 700 FREQUENCY (MHz) 800 900 1000
07806-024
0
50 100
Figure 10. Peak-to-Peak Output Voltage vs. Frequency, CMOS
55
Figure 13. Duty Cycle vs. Output Frequency, LVPECL and LVDS (15 pF Load)
54 5pF 10pF 20pF 53
DUTY CYCLE (%)
52
51
07806-025
07806-022
50 0 100 200 FREQUENCY (MHz) 300
200mV/DIV
500ps/DIV
Figure 11. Duty Cycle vs. Output Frequency, CMOS
Figure 14. Typical Output Waveform, LVPECL (805 MHz)
Rev. C | Page 10 of 32
07806-023
0
0.4
AD9552
100mV/DIV
07806-026
500mV/DIV
500ps/DIV
1.25ns/DIV
Figure 15. Typical Output Waveform, LVDS (805 MHz, 3.5 mA Drive Current)
Figure 16. Typical Output Waveform, CMOS (250 MHz, 15 pF Load)
Rev. C | Page 11 of 32
07806-027
AD9552 INPUT/OUTPUT TERMINATION RECOMMENDATIONS
0.1F
AD9552
3.3V DIFFERENTIAL OUTPUT (LVDS OR LVPECL MODE) HIGH IMPEDANCE INPUT 0.1F
07806-028
AD9552
100 100
DOWNSTREAM DEVICE
Figure 17. AC-Coupled LVDS or LVPECL Output Driver
Figure 18. DC-Coupled LVDS or LVPECL Output Driver
Rev. C | Page 12 of 32
07806-029
3.3V DIFFERENTIAL OUTPUT (LVDS OR LVPECL MODE)
DOWNSTREAM DEVICE
AD9552 THEORY OF OPERATION
LOCKED FILTER DETECTOR LOCK DETECT
AD9552
2 OUT2
4 TO 11 1 TO 63
REFA XTAL TUNING CONTROL XTAL N1 2x PFD CHARGE PUMP
3350MHz TO 4050MHz
VCO
2 P0 P1 OUT1
N = 4N1 + N0 4 OR 5
SERIAL PORT
3 REGISTER BANK 3
- MODULATOR MOD, FRAC
N
A2:0 Y5:0
Figure 19. Detailed Block Diagram
PRESET FREQUENCY RATIOS
The frequency selection pins (A[2:0] and Y[5:0]) allow the user to hardwire the device for preset input and output divider values based on the pin logic states (see Figure 19). The pins decode ground or open connections as Logic 0 or Logic 1, respectively. Use the serial I/O port to change the divider values from the preset values provided by the A[2:0] and Y[5:0] pins. The A[2:0] pins select one of eight input reference frequencies (see Table 9). The user supplies the input reference frequency by connecting a single-ended clock signal to the REF pin or a crystal resonator across the XTAL pins. If the A[2:0] pins select 10 MHz, 12 MHz, 12.8 MHz, or 16 MHz, the input frequency to the AD9552 doubles internally. Alternatively, if Register 0x1D[2] is set to 1, the input frequency doubles. Table 9. Input Reference Frequency Selection Pins
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Reference Frequency (MHz) 10.00 12.00 12.80 16.00 19.20 19.44 20.00 26.00
The Y[5:0] pins select the appropriate feedback and output dividers to synthesize the output frequencies (see Table 10). The output frequencies provided in Table 10 are exact; that is, the number of decimal places displayed is sufficient to maintain full precision. Where a decimal representation is not practical, a fractional multiplier is used. The VCO and output frequency shift in frequency by a ratio of the reference frequency used vs. the frequency specified in Table 9. Note that the VCO frequency must stay within the minimum and maximum range specified in Table 1. Typically, the selection of the VCO frequency band, as well as the gain adjustment, by the external pin strap occurs as part of the device's automatic VCO calibration process, which initiates at power up (or reset). If the user changes the VCO frequency band via the SPI interface, however, a forced VCO calibration should be initiated by first enabling SPI control of the VCO calibration (Register 0x0E[2] = 1) and then writing a 1 to the calibrate VCO bit (Register 0x0E[7]).
Rev. C | Page 13 of 32
07806-006
6
PRECONFIGURED DIVIDER VALUES
N, MOD, FRAC, P0, P1
P0, P1
AD9552
Table 10. Output Frequency Selection Pins
Y5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Y4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Y3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 Y2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 Y1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 Y0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCO Frequency (MHz) 3732.48 3888 3840 3932.16 3750 3733.296 3560.439 3564 3732.48 3932.16 4000 3825 3840 4000 3724 3732.48 3750 3825 3867.188 3944.531 3999.086 4015.959 4023.878 3554.742 3932.16 4000 3732.48 3840 4000 3471.4 3718.75 3763.2 3984.375 3732.48 3748.229 3750 3763.978 3779.927 3840 3849.12 3867.188 3944.531 3961.105 3999.086 4014.769 4015.959 4017.857 4025.032 4032.976 3452.846 3467.415 3468.75 3481.996 3521.903 Output (MHz) 51.84 54 60 61.44 62.5 66.666 74.17582 74.25 77.76 98.304 100 106.25 120 125 133 155.52 156.25 159.375 161.1328125 10518.75/64 155.52 x (15/14) 155.52 x (255/237) 167.6616 177.7371 245.76 250 311.04 320 400 433.925 531.25 537.6 569.1964 622.08 624.7048 625 622.08 x (239/237) 629.9878 640 641.52 625 x (66/64) 657.421875 657.421875 x (239/238) 622.08 x (15/14) 669.1281 622.08 x (255/237) 625 x (15/14) 670.8386 622.08 x (255/236) 625 x (66/64) x (15/14) 625 x (255/237) x (66/64) 693.75 622.08 x (253/226) 657.421875 x (255/238)
Rev. C | Page 14 of 32
AD9552
Y5 1 1 1 1 1 1 1 1 1 1 Y4 1 1 1 1 1 1 1 1 1 1 Y3 0 0 1 1 1 1 1 1 1 1 Y2 1 1 0 0 0 0 1 1 1 1 Y1 1 1 0 0 1 1 0 0 1 1 Y0 0 1 0 1 0 1 0 1 0 1 VCO Frequency (MHz) 3536.763 3582.686 3593.75 3598.672 3740.355 3750 3888 3897.843 3906.25 4028.32 Output (MHz) 657.421875 x (255/237) 716.5372 718.75 719.7344 748.0709 750 777.6 779.5686 781.25 625 x (10/8) x (66/64)
COMPONENT BLOCKS
Input Reference
The AD9552 offers the following input reference options: * * Crystal resonator connected directly across the XTAL pins CMOS-compatible, single-ended clock source connected directly to the REF pin
Reference Monitor
The REF input includes a monitor circuit that detects signal presence at the REF input. If the device detects a clock signal on the REF pin, it automatically selects the REF input as the input reference source and shuts down the crystal oscillator. This automatic preference for a REF input signal is the default mode of operation. However, the user can override the default setting via Register 0x1D[0]. Setting this bit forces the device to override the signal detector associated with the REF input and activates the crystal oscillator (whether or not a REF input signal is present).
In the case of a crystal resonator, the AD9552 expects a crystal with a specified load capacitance of 15 pF (default). The AD9552 provides the load capacitance internally. The internal load capacitance consists of a fixed component of 13 pF and a variable (programmable) component of 0 pF to 15.75 pF. After applying power to the AD9552 (or after a device reset), the programmable component assumes a value of 2 pF. This establishes the default load capacitance of 15 pF. To accommodate crystals with a specified load capacitance other than 15 pF (8 pF to 23.75 pF), the user can adjust the programmable capacitance in 0.25 pF increments via Register 0x1B[5:0]. Note that when the user sets Register 0x1B[7] to 0 (enabling SPI control of the XTAL tuning capacitors), the variable capacitance changes from 2 pF (its power-up value) to 15.75 pF due to the default value of Register 0x1B[5:0]. This causes the crystal load capacitance to be 23.75 pF until the user overwrites the default contents of Register 0x1B[5:0]. A noncomprehensive, alphabetical list of crystal manufacturers includes the following: * * * * * * AVX/Kyocera ECS Epson Toyocom Fox Electronics NDK Siward
2x Frequency Multiplier
The 2x frequency multiplier provides the option to double the frequency delivered by either the REF or XTAL input. This allows the user to take advantage of a higher frequency delivered to the PLL, which allows for greater separation between the frequency generated by the PLL and the associated reference spur. However, increased reference spur separation comes at the expense of the harmonic spurs introduced by the frequency multiplier. As such, beneficial use of the frequency multiplier is application specific.
PLL
The PLL consists of a phase/frequency detector (PFD), a partially integrated analog loop filter (see Figure 20), an integrated voltage-controlled oscillator (VCO), and a feedback divider with an optional third-order SDM that allows for fractional divide ratios. The PLL produces a nominal 3.7 GHz signal that is phase-locked to the input reference signal. The loop bandwidth of the PLL is nominally 50 kHz. The PFD of the PLL drives a charge pump that automatically changes current proportionately to the feedback divider value. This increase or decrease in current maintains a constant loop bandwidth with changes in the input reference or the output frequency.
FROM CHARGE PUMP 2.5k 1.25k 105pF 1.25k 15pF 2.5k 15pF 20pF TO VCO
The AD9552 evaluation board functions with the NDK NX3225SA crystal or with the Siward 571200-A258-001 crystal. Although these crystals meet the load capacitance and motional resistance requirements of the AD9552 according to their data sheets, Analog Devices, Inc., does not guarantee their operation with the AD9552, nor does Analog Devices endorse one supplier of crystals over another.
16
EXTERNAL LOOP FILTER CAPACITOR
Figure 20. Internal Loop Filter
Rev. C | Page 15 of 32
07806-004
AD9552
The gain of the PLL is proportional to the current delivered by the charge pump. The user can override the default charge pump current setting, and, thereby, the PLL gain, by using Register 0x0A[7:0]. The PLL has a VCO with 128 frequency bands spanning a range of 3350 MHz to 4050 MHz (3700 MHz nominal). However, the actual operating frequency within a particular band depends on the control voltage that appears on the loop filter capacitor. The control voltage causes the VCO output frequency to vary linearly within the selected band. This frequency variability allows the control loop of the PLL to synchronize the VCO output signal with the reference signal applied to the PFD. Typically, selection of the VCO frequency band (as well as gain adjustment) occurs automatically as part of the device's automatic VCO calibration process, which initiates at power up (or reset). Alternatively, the user can force VCO calibration by first enabling SPI control of VCO calibration (Register 0x0E[2] = 1) and then writing a 1 to the calibrate VCO bit (Register 0x0E[7]). To facilitate system debugging, the user can override the VCO band setting by first enabling SPI control of VCO band (Register 0x0E[0] = 1) and then writing the desired value to Register 0x10[7:1]. The PLL has a feedback divider coupled with a third-order SDM that enables the PLL to provide integer-plus-fractional frequency upconversion. The integer factor, N, is variable via an 8-bit programming register. The range of N is from NMIN to 255, where NMIN is 36 or 47 depending on whether the SDM is disabled or enabled, respectively. The SDM in the feedback path allows for a fractional divide value that takes the form of N + F/M, where N is the integer part (eight bits), M is the modulus (20 bits), and F is the fractional part (20 bits), with all three parameters being positive integers. The feedback SDM gives the AD9552 the ability to support a wide range of output frequencies with exact frequency ratios relative to the input reference.
Output Drivers
The user has control over the following output driver parameters via the programming registers: * * * * Logic family and pin functionality Polarity (for CMOS family only) Drive current Power-down
The logic families are LVDS, LVPECL, and CMOS. Selection of the logic family is via the mode control bits in the OUT1 driver control register (Register 0x32[5:3]) and the OUT2 driver control register (Register 0x34[5:3]), as detailed in Table 11. Regardless of the selected logic family, each output driver uses two pins: OUT1 and OUT1 are used by one driver, and OUT2 and OUT2 are used by the other. This enables support of the differential signals associated with the LVDS and LVPECL logic families. CMOS, on the other hand, is a single-ended signal requiring only one output pin, but both output pins are available for optional provision of a dual, single-ended CMOS output clock. Refer to the first entry (CMOS (both pins)) in Table 11. Table 11. Output Channel Logic Family and Pin Functionality
Mode Control Bits[2:0] 000 001 010 011 100 101 110 111 Logic Family and Pin Functionality CMOS (both pins) CMOS (positive pin), tristate (negative pin) Tristate (positive pin), CMOS (negative pin) Tristate (both pins) LVDS LVPECL Undefined Undefined
If the mode bits indicate the CMOS logic family, the user has control of the logic polarity associated with each CMOS output pin via the OUT1 and OUT2 driver control registers. If the mode bits indicate the CMOS or LVDS logic family, the user can select whether the output driver uses weak or strong drive capability via the OUT1 and OUT2 driver control registers. In the case of the CMOS family, the strong setting allows for driving increased capacitive loads. In the case of the LVDS family, the nominal weak and strong drive currents are 3.5 mA and 7 mA, respectively. The OUT1 and OUT2 driver control registers also have a powerdown bit to enable/disable the output drivers. The power-down function is independent of the logic family selection. Note that, unless the user programs the device to allow SPI port control of the output drivers, the drivers default to LVPECL or LVDS, depending on the logic level on the OUTSEL pin (Pin 15). For OUTSEL = 0, both outputs are LVDS. For OUTSEL = 1, both outputs are LVPECL. In the pin-selected LVDS mode, the user can still control the drive strength, using the SPI port.
PLL Locked Indicator
The PLL provides a status indicator that appears at an external pin (LOCKED). The indicator shows when the PLL has acquired a locked condition.
Output Dividers
Two integer dividers exist in the output chain. The first divider (P0) yields an integer submultiple of the VCO frequency. The second divider (P1) establishes the frequency at OUT1 as an integer submultiple of the output frequency of the P0 divider.
Input-to-OUT2 Option
By default, OUT2 delivers an output frequency that is the same frequency as OUT1. However, the user has the option of making OUT2 a replica of the input frequency (REF or XTAL) by programming Register 33[3] = 1.
Rev. C | Page 16 of 32
AD9552
PART INITIALIZATION AND AUTOMATIC POWERON RESET
The AD9552 has an internal power-on reset circuit. At power-up, internal logic relies on the internal reference monitor to select either the crystal oscillator or the reference input and then initiates VCO calibration using whichever is found. If both are present, the external reference path is chosen. VCO calibration is required in order for the device to lock. If the input reference signal is not present, VCO calibration waits until a valid input reference is present. As soon as an input reference signal is present, VCO calibration starts. If the user wishes to use the crystal oscillator input even if the reference input is present, the user needs to set Bit 0 (use crystal resonator) in Register 0x1D. Any change to the preset frequency selection pins or the PLL divide ratios requires the user to recalibrate the VCO. The frequency at the input to the PFD (fPFD) is calculated as follows: fPFD = K x fREF The operating range of the VCO (3.35 GHz fVCO 4.05 GHz) places the following constraint on fPFD:
3350 N + FRAC MOD MHz f PFD 4050 N + FRAC MOD MHz
CALCULATING DIVIDER VALUES
This section provides a three-step procedure for calculating the divider values when given a specific fOUT1/fREF ratio (fREF is the frequency of either the REF input signal source or the external crystal resonator). The computation process is described in general terms, but a specific example is provided for clarity. The example is based on a frequency control pin setting of A[2:0] = 111 (see Table 9) and Y[5:0] = 101000 (see Table 10), yielding the following: fREF = 26 MHz fOUT1 = 625 x (66/64) MHz 1. Determine the output divide factor (ODF). Note that the VCO frequency (fVCO) spans 3350 MHz to 4050 MHz. The ratio, fVCO/fOUT1, indicates the required ODF. Given the specified value of fOUT1 (~644.53 MHz) and the range of fVCO, the ODF spans a range of 5.2 to 6.3. The ODF must be an integer, which means that ODF = 6 (because 6 is the only integer between 5.2 and 6.3). 2. Determine suitable values for P0 and P1. The ODF is the product of the two output dividers, so ODF = P0P1. It has already been determined that ODF = 6 for the given example. Therefore, P0P1 = 6 with the constraints that P0 and P1 are both integers and that 4 P0 11 (see the Output/Input Frequency Relationship section). These constraints lead to the single solution: P0 = 6 and P1 = 1. Although this particular example yields a single solution for the output divider values with fOUT1 644.53 MHz, some fOUT1 frequencies result in multiple ODFs rather than just one. For example, if fOUT1 = 100 MHz the ODF ranges from 34 to 40. This leads to an assortment of possible values for P0 and P1, as shown in Table 12. Table 12. Combinations for P0 and P1
P0 4 4 5 5 6 7 8 9 10 P1 9 10 7 8 6 5 5 4 4 ODF (P0 x P1) 36 40 35 40 36 35 40 36 40
OUTPUT/INPUT FREQUENCY RELATIONSHIP
The frequency at OUT1 and OUT2 is a function of the PLL feedback divider values (N, FRAC, and MOD) and the output divider values (P0 and P1). The equations that define the frequency at OUT1 and OUT2 (fOUT1 and fOUT2, respectively) are as follows.
N+ f OUT 1 = f REF K x P0 P1
FRAC MOD

fOUT2 = fOUT1 where: fREF is the input reference or crystal resonator frequency. K is the input mode scale factor. N is the integer feedback divider value. FRAC and MOD are the fractional feedback divider values. P0 and P1 are the OUT1 divider values. The numerator of the fOUT1 equation contains the feedback division factor, which has an integer part (N) due to an integer divider along with an optional fractional part (FRAC/MOD) associated with the feedback SDM. The following constraints apply:
N {N MIN , N MIN + 1,L, 255} FRAC {0, 1, L, 1,048,575} K { , 2} 1 MOD { , 2 , L, 1,048,575} 1
N MIN {36 , 47}
P1 { , 2,L, 63} 1
P0 {4 , 5,L,11}
Note that NMIN and K can each be one of two values. The value of NMIN depends on the state of the SDM. NMIN = 36 when the SDM is disabled or NMIN = 47 when it is enabled. The value of K depends on the 2x frequency multiplier. K = 1 when the 2x frequency multiplier is bypassed, or K = 2 when it is enabled.
Rev. C | Page 17 of 32
AD9552
The P0 and P1 combinations listed in Table 12 are all equally valid. However, note that they yield only three valid ODF values (35, 36, and 40) from the original range of 34 to 40. 3. Determine the feedback divider values for the PLL. Repeat this step for each ODF when multiple ODFs exist (for example, 35, 36, and 40 in the case of Table 12). To calculate the feedback divider values for a given ODF, use the following equation:
f OUT 1 f REF X x ODF = Y
In the example, N = 148 and R/Y = 1228/1664, which reduces to R/Y = 307/416. These values of N, R, and Y constitute the following respective feedback divider values: N = 148, FRAC = 307, and MOD = 416. The only caveat is that N and MOD must meet the constraints given in the Output/Input Frequency Relationship section. In the example, FRAC is nonzero, so the division value is an integer plus the fractional component, FRAC/MOD. This implies that the feedback SDM is necessary as part of the feedback divider. If FRAC = 0, the feedback division factor is an integer and the SDM is not required (it can be bypassed). Although the feedback divider values obtained in this way provide the proper feedback divide ratio to synthesize the exact output frequency, they may not yield optimal jitter performance at the final output. One reason for this is that the value of MOD defines the period of the SDM, which has a direct impact on the spurious output of the SDM. Specifically, in the spectral band from dc to fPFD, the SDM exhibits spurs at intervals of fPFD/ MOD. Thus, the spectral separation (f) of the spurs associated with the feedback SDM is
f = f PFD MOD
Note that the left side of the equation contains variables with known quantities. Furthermore, the values are necessarily rational, so the left side is expressible as a ratio of two integers, X and Y. Following is an example equation.
66 625 64 x 6 = 625(66)(6) = 247,500 = X 26 Y 26(64) 1664 In the context of the AD9552, X/Y is always an improper fraction. Therefore, it is expressible as the sum of an integer, N, and the proper fraction, R/Y (R and Y are integers).
X R =N+ Y Y
247,500 R =N+ 1664 Y
This particular example yields N = 148, Y = 1664, and R = 1228. To arrive at this result, use long division to convert the improper fraction, X/Y, to an integer (N) and a proper fraction (R/Y). Note that dividing Y into X by means of long division yields an integer, N, and a remainder, R. The proper fraction has a numerator (R, the remainder) and a denominator (Y, the divisor), as shown in Figure 21.
N YX -NY R
07806-005
Because the SDM is in the feedback path of the PLL, these spurs appear in the output signal as spurious components offset by f from fOUT1. Therefore, a small MOD value pro-duces relatively large spurs with relatively large frequency offsets from fOUT1, whereas a large MOD value produces smaller spurs but more closely spaced to fOUT1. Clearly, the value of MOD has a direct impact on the spurious content (that is, jitter) at OUT1. Generally, the largest possible MOD value yields the smallest spurs. Thus, it is desirable to scale MOD and FRAC by the integer part of 220 divided by the value of MOD obtained previously. In the example, the value of MOD is 416, yield-ing a scale factor of 2520 (the integer part of 220/416). A scale factor of 2520 leads to FRAC = 307 x 2520 = 773,640 and MOD = 416 x 2520 = 1,048,320.
X R =N+ Y Y
LOW DROPOUT (LDO) REGULATORS
The AD9552 is powered from a single 3.3 V supply and contains on-chip LDO regulators for each function to eliminate the need for external LDOs. To ensure optimal performance, each LDO output should have a 0.47 F capacitor connected between its access pin and ground, and this capacitor should be kept as close to the device as possible.
Figure 21. Example Long Division
It is imperative that long division be used to obtain the correct results. Avoid the use of a calculator or math program, because these do not always yield correct results due to internal rounding and/or truncation. Some calculators or math programs may be up to the task if they can handle very large integer operations, but such are not common.
Rev. C | Page 18 of 32
AD9552 APPLICATIONS INFORMATION
THERMAL PERFORMANCE
Table 13. Thermal Parameters for the 32-Lead LFCSP Package
Symbol JA JMA JMA JB JC JT
1 2
Thermal Characteristic Using a JEDEC51-7 Plus JEDEC51-5 2S2P Test Board 1 Junction-to-ambient thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-2 (still air) Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-ambient thermal resistance, 2.5 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-board thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-8 (moving air) Junction-to-case thermal resistance (die-to-heat sink) per MIL-Std 883, Method 1012.1 Junction-to-top-of-package characterization parameter, 0 m/sec airflow per JEDEC JESD51-2 (still air)
Value 2 40.5 35.4 31.8 23.3 4.2 0.4
Unit C/W C/W C/W C/W C/W C/W
The exposed pad on the bottom of the package must be soldered to ground to achieve the specified thermal performance. Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the application to determine whether they are similar to those assumed in these calculations.
The AD9552 is specified for a case temperature (TCASE). To ensure that TCASE is not exceeded, an airflow source can be used. Use the following equation to determine the junction temperature on the application PCB: TJ = TCASE + (JT x PD) where: TJ is the junction temperature (C). TCASE is the case temperature (C) measured by the customer at the top center of the package. JT is the value indicated in Table 13. PD is the power dissipation (see the Specifications section).
Values of JA are provided for package comparison and PCB design considerations. JA can be used for a first-order approximation of TJ using the following equation: TJ = TA + (JA x PD) where TA is the ambient temperature (C). Values of JC are provided for package comparison and PCB design considerations when an external heat sink is required. Values of JB are provided for package comparison and PCB design considerations.
Rev. C | Page 19 of 32
AD9552 SERIAL CONTROL PORT
The AD9552 serial control port is a flexible, synchronous, serial communications port that allows an easy interface to many industry-standard microcontrollers and microprocessors. Single or multiple byte transfers are supported, as well as MSB first or LSB first transfer formats. The AD9552 serial control port is configured for a single bidirectional I/O pin (SDIO only). The serial control port has two types of registers: read-only and buffered. Read-only registers are nonbuffered and ignore write commands. All writable registers are buffered (also referred to as mirrored) and require an I/O update to transfer the new values from a temporary buffer on the chip to the actual register. To invoke an I/O update, write a 1 to the I/O update bit found in Register 0x05[0]. Because any number of bytes of data can be changed before issuing an update command, the update simultaneously enables all register changes occurring since any previous update. the serial control port state machine enters a wait state until all data has been sent. If the system controller decides to abort before the complete transfer of all the data, the state machine must be reset either by completing the remaining transfer or by returning the CS line low for at least one complete SCLK cycle (but fewer than eight SCLK cycles). A rising edge on the CS pin on a nonbyte boundary terminates the serial transfer and flushes the buffer.
Table 14. Byte Transfer Count
W1 0 0 1 1 W0 0 1 0 1 Bytes to Transfer (Excluding the 2-Byte Instruction) 1 2 3 Streaming mode
SERIAL CONTROL PORT PIN DESCRIPTIONS
SCLK (serial data clock) is the serial shift clock. This pin is an input. SCLK is used to synchronize serial control port reads and writes. Write data bits are registered on the rising edge of this clock, and read data bits are registered on the falling edge. This pin is internally pulled down by a 30 k resistor to ground. SDIO (digital serial data input/output) is a dual-purpose pin that acts as input only or as an input/output. The AD9552 defaults to bidirectional pins for I/O. CS (chip select bar) is an active low control that gates the read and write cycles. When CS is high, SDIO is in a high impedance state. This pin is internally pulled up by a 100 k resistor to 3.3 V. It should not be left floating. See the Operation of the Serial Control Port section on the use of the CS pin in a communication cycle.
SCLK SDIO
13
In the streaming mode (Bits[W1:W0] = 11), any number of data bytes can be transferred in a continuous stream. The register address is automatically incremented or decremented (see the MSB/LSB First Transfers section). CS must be raised at the end of the last byte to be transferred, thereby ending the stream mode.
Communication Cycle--Instruction Plus Data
There are two parts to a communication cycle with the AD9552. The first part writes a 16-bit instruction word into the AD9552, coincident with the first 16 SCLK rising edges. The instruction word provides the AD9552 serial control port with information regarding the data transfer, which is the second part of the communication cycle. The instruction word defines whether the upcoming data transfer is a read or a write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer.
Write
If the instruction word is for a write operation (Bit I15 = 0), the second part is the transfer of data into the serial control port buffer of the AD9552. The length of the transfer (1, 2, or 3 bytes; or streaming mode) is indicated by two bits (Bits[W1:W0]) in the instruction byte. The length of the transfer indicated by (Bits[W1:W0]) does not include the 2-byte instruction. CS can be raised after each sequence of eight bits to stall the bus (except after the last byte, where it ends the cycle). When the bus is stalled, the serial transfer resumes when CS is lowered. Stalling on nonbyte boundaries resets the serial control port.
AD9552
SERIAL CONTROL PORT
07806-006
14
CS
12
Figure 22. Serial Control Port
OPERATION OF THE SERIAL CONTROL PORT
Framing a Communication Cycle with CS
The CS line gates the communication cycle (a write or a read operation). CS must be brought low to initiate a communication cycle. The CS stall high function is supported in modes where three or fewer bytes of data (plus instruction data) are transferred. Bits[W1:W0] must be set to 00, 01, or 10 (see Table 14). In these modes, CS may temporarily return high on any byte boundary, allowing time for the system controller to process the next byte. CS can go high on byte boundaries only and can go high during either part (instruction or data) of the transfer. During this period,
Read
If the instruction word is for a read operation (Bit I15 = 1), the next N x 8 SCLK cycles clock out the data from the address specified in the instruction word, where N is 1, 2, 3, or 4, as determined by Bits[W1:W0]. In this case, 4 is used for streaming mode, where four or more words are transferred per read. The data read back is valid on the falling edge of SCLK. The default mode of the AD9552 serial control port is bidirectional mode, and the data read back appears on the SDIO pin.
Rev. C | Page 20 of 32
AD9552
By default, a read request reads the register value that is currently in use by the AD9552. However, setting Register 0x04[0] = 1 causes the buffered registers to be read instead. The buffered registers are the ones that take effect during the next I/O update.
SCLK SDIO
13
MSB/LSB FIRST TRANSFERS
The AD9552 instruction word and byte data can be MSB first or LSB first. The default for the AD9552 is MSB first. The LSB first mode can be set by writing a 1 to Register 0x00[6] and requires that an I/O update be executed. Immediately after the LSB first bit is set, all serial control port operations are changed to LSB first order. When MSB first mode is active, the instruction and data bytes must be written from MSB to LSB. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes must follow in order from high address to low address. In MSB first mode, the serial control port internal address generator decrements for each data byte of the multibyte transfer cycle. When LSB first = 1 (LSB first), the instruction and data bytes must be written from LSB to MSB. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. The serial control port internal byte address generator increments for each data byte of the multibyte transfer cycle. The AD9552 serial control port register address decrements from the register address just written toward 0x00 for multibyte I/O operations if the MSB first mode is active (default). If the LSB first mode is active, the serial control port register address increments from the address just written toward 0x34 for multibyte I/O operations. Unused addresses are not skipped during multibyte I/O operations. The user should write the default value to a reserved register and should write only zeros to unmapped registers. Note that it is more efficient to issue a new write command than to write the default value to more than two consecutive reserved (or unmapped) registers.
14
SERIAL CONTROL PORT
CONTROL REGISTERS
REGISTER BUFFERS
REGISTER UPDATE EXECUTE AN INPUT/OUTPUT UPDATE
AD9552
CORE
Figure 23. Relationship Between the Serial Control Port Register Buffers and the Control Registers
The AD9552 uses Register 0x00 to Register 0x34. Although the AD9552 serial control port allows both 8-bit and 16-bit instructions, the 8-bit instruction mode provides access to five address bits (Address Bits[A4:A0]) only, which restricts its use to Address Space 0x00 to Address Space 0x01. The AD9552 defaults to 16-bit instruction mode on power-up, and the 8-bit instruction mode is not supported.
INSTRUCTION WORD (16 BITS)
The MSB of the instruction word (see Table 15) is R/W, which indicates whether the instruction is a read or a write. The next two bits, W1 and W0, are the transfer length in bytes. The final 13 bits are the address bits (Address Bits[A12:A0]) at which the read or write operation is to begin. For a write, the instruction word is followed by the number of bytes of data indicated by Bits[W1:W0], which is interpreted according to Table 14. Address Bits[A12:A0] select the address within the register map that is written to or read from during the data transfer portion of the communication cycle. The AD9552 uses all of the 13-bit address space. For multibyte transfers, this address is the starting byte address.
Table 15. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB I15 R/W I14 W1 I13 W0 I12 A12 I11 A11 I10 A10 I9 A9 I8 A8
07806-007
CS
12
I7 A7
I6 A6
I5 A5
I4 A4
I3 A3
I2 A2
I1 A1
LSB I0 A0
Table 16. Definition of Terms Used in Serial Control Port Timing Diagrams
Parameter tCLK tDV tDS tDH tS tH tHIGH tLOW Description Period of SCLK Read data valid time (time from falling edge of SCLK to valid data on SDIO) Setup time between data and rising edge of SCLK Hold time between data and rising edge of SCLK Setup time between CS and SCLK Hold time between CS and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state
Rev. C | Page 21 of 32
AD9552
CS SCLK DON'T CARE SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE DON'T CARE
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N - 1) D ATA
Figure 24. Serial Control Port Write--MSB First, 16-Bit Instruction, Two Bytes Data
CS SCLK DON'T CARE SDIO DON'T CARE
07806-009 07806-012
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N - 1) D ATA
REGISTER (N - 2) D ATA
REGISTER (N - 3) D ATA
Figure 25. Serial Control Port Read--MSB First, 16-Bit Instruction, Four Bytes Data
tHIGH tDH tLOW
DON'T CARE DON'T CARE
tDS tS
CS SCLK
tCLK
tH
SDIO
Figure 26. Serial Control Port Write--MSB First, 16-Bit Instruction, Timing Measurements
CS
SCLK
07806-011
tDV
SDIO DATA BIT N DATA BIT N - 1
Figure 27. Timing Diagram for Serial Control Port Register Read
CS SCLK DON'T CARE SDIO DON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 DON'T CARE DON'T CARE
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N + 1) D ATA
Figure 28. Serial Control Port Write--LSB First, 16-Bit Instruction, Two Bytes Data
tS
CS
tH
tCLK tHIGH
SCLK
tLOW
tDS
tDH
SDIO BIT N BIT N + 1
07806-013
Figure 29. Serial Control Port Timing--Write
Rev. C | Page 22 of 32
07806-010
DON'T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
DON'T CARE
07806-008
AD9552 REGISTER MAP
A bit that is labeled "aclr" is an active high, autoclearing bit. When set to a Logic 1 state, the control logic automatically returns it to a Logic 0 state upon completion of the indicated task.
Table 17. Register Map
Addr. (Hex) 0x00 0x04 0x05 0x0A Register Name Serial port control Readback control I/O update PLL charge pump and PFD control PLL charge pump and PFD control PLL charge pump and PFD control PLL charge pump and PFD control VCO control (MSB) Bit 7 0 Unused Unused Bit 6 LSB first Unused Unused Bit 5 Soft reset (aclr) Unused Unused Bit 4 1 Unused Unused Bit 3 1 Unused Unused Bit 2 Soft reset Unused Unused Bit 1 LSB first Unused Unused (LSB) Bit 0 0 Readback control I/O update (aclr) Default 0x18 0x00 0x00 0x80
Charge pump current control[7:0] (3.5 A granularity, ~900 A full scale)
0x0B
0x0C
Enable SPI control of charge pump current Unused
Enable SPI control of antibacklash period CP offset current polarity
CP mode[1:0]
Enable CP mode control
PFD feedback input edge control Reserved
PFD reference input edge control Reserved
Force VCO to midpoint frequency Reserved
0x30
CP offset current[1:0]
0x0D
Antibacklash control[1:0]
Unused
Unused
Enable CP offset current control Unused
0x00
Unused
Unused
0x0E
Calibrate VCO (aclr)
Enable ALC
ALC threshold[2:0]
Enable SPI control of VCO calibration
Boost VCO supply
0x0F 0x10 0x11 0x12 0x13 0x14
VCO control VCO control PLL control PLL control PLL control PLL control
VCO level control[5:0] VCO band control[6:0] N[7:0] (SDM integer part) MOD[19:12] (SDM modulus) MOD[11:4] (SDM modulus) MOD[3:0] (SDM modulus) Enable SPI Bypass SDM control of output frequency FRAC[19:12] (SDM fractional part) FRAC[11:4] (SDM fractional part) FRAC[3:0] (SDM fractional part) Unused Unused P1 divider[4:0] Enable SPI Unused Unused control of OUT1 dividers Receiver Band gap voltage adjust[4:0] reset (aclr) (00000 = maximum, 11111 = minimum)
Unused
PLL lock detector powerdown Enable SPI control of VCO band setting Unused Unused
0x00
0x70
0x80 0x80 0x00 0x80 0x00 0x00
Disable SDM
Reset PLL
0x15 0x16 0x17 0x18 0x19
PLL control PLL control PLL control PLL control PLL control
Unused P0 divider[2:0]
P1 divider[5]
0x20 0x00 0x01 0x00 0x20
0x1A
Input receiver and band gap XTAL tuning control
Unused
Enable SPI control of band gap voltage
0x00
0x1B
Disable SPI control of XTAL tuning capacitance
Unused
XTAL tuning capacitor control[5:0] (0.25 pF per bit, inverted binary coding)
0x80
Rev. C | Page 23 of 32
AD9552
Addr. (Hex) 0x1C 0x1D Register Name XTAL control XTAL control OUT1 driver control (MSB) Bit 7 Unused Unused Bit 6 Unused Unused Bit 5 Unused Unused Bit 4 Unused Unused Bit 3 Unused Unused Bit 2 Unused Bit 1 Unused (LSB) Bit 0 Unused Use crystal resonator Enable SPI control of OUT1 driver control Unused Enable SPI control of OUT2 driver control Default 0x00 0x00
0x32
OUT1 drive strength
OUT1 powerdown
OUT1 mode control[2:0]
Select 2x Unused frequency multiplier OUT1 CMOS polarity[1:0]
0xA8
0x33 0x34
Select OUT2 source OUT2 driver control
Unused OUT2 drive strength
Unused OUT2 powerdown
Unused
OUT2 source OUT2 mode control[2:0]
Unused
Unused
Unused
0x00 0xA8
OUT2 CMOS polarity[1:0]
REGISTER MAP DESCRIPTIONS
Control bit functions are active high unless stated otherwise. Register address values are always hexadecimal unless otherwise indicated.
Serial Port Control (Register 0x00 to Register 0x05)
Table 18.
Address 0x00 Bit 7 6 Bit Name Unused LSB first Description Forced to Logic 0 internally, which enables 3-wire mode only. Bit order for SPI port. 0 = most significant bit and byte first (default). 1 = least significant bit and byte first. Software initiated reset (register values set to default). This is an autoclearing bit. Forced to Logic 1 internally, which enables 16-bit mode (the only mode supported by the device). Mirrored version of the contents of Register 0x00[7:4] (that is, Bits[3:0] = Bits[7:4]). Unused. For buffered registers, serial port readback reads from actual (active) registers instead of from the buffer. 0 = reads values currently applied to the internal logic of the device (default). 1 = reads buffered values that take effect on next assertion of I/O update. Unused. Writing a 1 to this bit transfers the data in the serial I/O buffer registers to the internal control registers of the device. This is an autoclearing bit.
5 4 [3:0] [7:1] 0
Soft reset Unused Unused Unused Readback control
0x04
0x05
[7:1] 0
Unused I/O update
Rev. C | Page 24 of 32
AD9552
PLL Charge Pump and PFD Control (Register 0x0A to Register 0x0D)
Table 19.
Address 0x0A Bit [7:0] Bit Name Charge pump current control Description These bits set the magnitude of the PLL charge pump current. The granularity is ~3.5 A with a full-scale magnitude of ~900 A. Register 0x0A is ineffective unless Register 0x0B[7] = 1. Default is 0x80, or ~448 A. Controls functionality of Register 0x0A. 0 = the device automatically controls the charge pump current (default). 1 = charge pump current defined by Register 0x0A. Controls functionality of Register 0x0D[7:6]. 0 = the device automatically controls the antibacklash period (default). 1 = antibacklash period defined by Register 0x0D[7:6]. Controls the mode of the PLL charge pump. 00 = tristate. 01 = pump up. 10 = pump down. 11 = normal (default). Controls functionality of Bits[5:4] (CP mode). 0 = the device automatically controls the charge pump mode (default). 1 = charge pump mode is defined by Bits[5:4]. Selects the polarity of the active edge of the PLL's feedback input. 0 = positive edge (default). 1 = negative edge. Selects the polarity of the active edge of the PLL's reference input. 0 = positive edge (default). 1 = negative edge. Selects VCO control voltage functionality. 0 = normal VCO operation (default). 1 = force VCO control voltage to midscale. Unused. Selects the polarity of the charge pump offset current of the PLL. This bit is ineffective unless Bit 3 = 1. 0 = pump up (default). 1 = pump down. Controls the magnitude of the charge pump offset current of the PLL as a fraction of the value in Register 0x0A. This bit is ineffective unless Bit 3 = 1. 00 = 1/2 (default). 01 = 1/4. 10 = 1/8. 11 = 1/16. Controls functionality of Bits[6:4]. 0 = the device automatically controls charge pump offset current (default). 1 = charge pump offset current defined by Bits[6:4]. Controls the PFD antibacklash period of the PLL. These bits are ineffective unless Register 0x0B[6] = 1. 00 = minimum (default). 01 = low. 10 = high. 11 = maximum. Unused. Controls power-down of the PLL lock detector. 0 = lock detector active (default). 1 = lock detector powered down.
0x0B
7
Enable SPI control of charge pump current Enable SPI control of antibacklash period CP mode
6
[5:4]
3
Enable CP mode control
2
PFD feedback input edge control
1
PFD reference input edge control
0
Force VCO to midpoint frequency
0x0C
7 6
Unused CP offset current polarity
[5:4]
CP offset current
3
Enable CP offset current control
0x0D
2:0 [7:6]
Reserved Antibacklash control
[5:1] 0
Unused PLL lock detector power-down
Rev. C | Page 25 of 32
AD9552
VCO Control (Register 0x0E to Register 0x10)
Table 20.
Address 0x0E Bit 7 6 Bit Name Calibrate VCO Enable ALC Description Initiates VCO calibration (this is an autoclearing bit). This bit is ineffective unless Bit 2 = 1. Enables automatic level control (ALC) of the VCO. 0 = Register 0x0F[7:2] defines the VCO level. 1 = the device automatically controls the VCO level (default). Controls the VCO ALC threshold detector level from minimum (000) to maximum (111). The default is 110. Enables functionality of Bit 7. 0 = the device automatically performs VCO calibration (default). 1 = Bit 7 controls VCO calibration. Selects VCO supply voltage. 0 = normal supply voltage (default). 1 = increase supply voltage by 100 mV. Controls VCO band setting functionality. 0 = the device automatically selects the VCO band (default). 1 = VCO band defined by Register 0x10[7:1]. Controls the VCO amplitude from minimum (00 0000) to maximum (11 1111). The default is 10 0000. These bits are ineffective unless 0x0E[6] = 0. Unused. Controls the VCO frequency band from minimum (000 0000) to maximum (111 1111). The default is 100 0000. Unused.
[5:3]
ALC threshold
2
Enable SPI control of VCO calibration Boost VCO supply
1
0
Enable SPI control of VCO band setting VCO level control
0x0F
[7:2]
0x10
[1:0] [7:1] 0
Unused VCO band control Unused
PLL Control (Register 0x11 to Register 0x19)
Table 21.
Address 0x11 0x12 0x13 0x14 Bit [7:0] [7:0] [7:0] [7:4] 3 Bit Name N MOD MOD MOD Enable SPI control of output frequency Bypass SDM Description The 8-bit integer divide value for the SDM. Default is 0x00. Note that operational limitations impose a lower boundary of 64 (0x40) on N. Bits[19:12] of the 20-bit modulus of the SDM. Bits[11:4] of the 20-bit modulus of the SDM. Bits[3:0] of the 20-bit modulus of the SDM. Default is MOD = 1000 0000 0000 0000 0000 (524,288). Controls output frequency functionality. 0 = output frequency defined by the Y[3:0] pins (default). 1 = contents of Register 0x11 to Register 0x17 define output frequency via N, MOD, and FRAC. Controls bypassing of the SDM. 0 = allow integer-plus-fractional division (default). 1 = allow only integer division. Controls the SDM internal clocks. 0 = normal operation (SDM clocks active) (default). 1 = SDM disabled (SDM clocks stopped). Controls initialization of the PLL. 0 = normal operation (default). 1 = resets the counters and logic associated with the PLL but does not affect the output dividers. Bits[19:12] of the 20-bit fractional part of the SDM. Bits[11:4] of the 20-bit fractional part of the SDM. Bits[3:0] of the 20-bit fractional part of the SDM. Default is FRAC = 0010 0000 0000 0000 0000 (131,072). Write zeros to these bits when programming this register. Bit 5 of the 6-bit P1 divider for OUT1.
Rev. C | Page 26 of 32
2
1
Disable SDM
0
Reset PLL
0x15 0x16 0x17
[7:0] [7:0] [7:4] [3:1] 0
FRAC FRAC FRAC Unused P1 divider
AD9552
Address 0x18 Bit [7:3] [2:0] Bit Name P1 divider P0 divider Description Bits[4:0] of the 6-bit P1 divider for OUT1 (1 P1 63). Do not set these bits to 000000. Default is P1 = 10 0000 (32). The P1 bits are ineffective unless Register 0x19[7] = 1. The 3-bit P0 divider for OUT1. The P0 divide value is as follows: 000 = 4 (default). 001 = 5. 010 = 6. 011 = 7. 100 = 8. 101 = 9. 110 = 10. 111 = 11. The P0 bits are ineffective unless Register 0x19[7] = 1. Controls functionality of OUT1 dividers. 0 = OUT1 dividers defined by the Y[5:0] pins (default). 1 = contents of Register 0x17 and Register 0x18 define OUT1 dividers (P0 and P1). Unused.
0x19
7
Enable SPI control of OUT1 dividers Unused
[6:0]
Input Receiver and Band Gap Control (Register 0x1A)
Table 22.
Address 0x1A Bit 7 Bit Name Receiver reset Description Input receiver reset control. This is an autoclearing bit. 0 = normal operation (default). 1 = reset input receiver logic. Controls the band gap voltage setting from minimum (0 0000) to maximum (1 1111). Default is 0 0000. Unused. Enables functionality of Bits[6:2]. 0 = the device automatically selects receiver band gap voltage (default). 1 = Bits[6:2] define the receiver band gap voltage.
[6:2] 1 0
Band gap voltage adjust Unused Enable SPI control of band gap voltage
XTAL Control (Register 0x1B to Register 0x1D)
Table 23.
Address 0x1B Bit 7 Bit Name Disable SPI control of XTAL tuning capacitance Unused XTAL tuning capacitor control Unused Unused Select 2x frequency multiplier Description Disables functionality of Bits[5:0]. 0 = tuning capacitance defined by Bits[5:0]. 1 = the device automatically selects XTAL tuning capacitance (default). Unused. Capacitance value coded as inverted binary (0.25 pF per bit); that is, 111111 is 0 pF, 111110 is 0.25 pF, and so on. The default value, 000000, is 15.75 pF. Unused. Unused. Select/bypass the 2x frequency multiplier. 0 = bypassed (default). 1 = selected. Unused. Automatic external reference select override. 0 = the device automatically selects the external reference path if an external reference signal is present (default). 1 = the device uses the crystal resonator input whether or not an external reference signal is present.
6 [5:0] 0x1C 0x1D [7:0] [7:3] 2
1 0
Unused Use crystal resonator
Rev. C | Page 27 of 32
AD9552
OUT1 Driver Control (Register 0x32)
Table 24.
Address 0x32 Bit 7 Bit Name OUT1 drive strength Description Controls the output drive capability of the OUT1 driver. 0 = weak. 1 = strong (default). Controls power-down functionality of the OUT1 driver. 0 = OUT1 active (default). 1 = OUT1 powered down. OUT1 driver mode selection. 000 = CMOS, both pins active. 001 = CMOS, positive pin active, negative pin tristate. 010 = CMOS, positive pin tristate, negative pin active. 011 = CMOS, both pins tristate. 100 = LVDS. 101 = LVPECL (default). 110 = not used. 111 = not used. Selects the polarity of the OUT1 pins in CMOS mode. 00 = positive pin logic is true = 1, false = 0/negative pin logic is true = 0, false = 1 (default). 01 = positive pin logic is true = 1, false = 0/negative pin logic is true = 1, false = 0. 10 = positive pin logic is true = 0, false = 1/negative pin logic is true = 0, false = 1. 11 = positive pin logic is true = 0, false = 1/negative pin logic is true = 1, false = 0. These bits are ineffective unless Bits[5:3] select CMOS mode. Controls OUT1 driver functionality. 0 = OUT1 is LVDS or LVPECL, per the OUTSEL pin (Pin 15) (default). 1 = OUT1 functionality defined by Bits[7:1].
6
OUT1 power-down
[5:3]
OUT1 mode control
[2:1]
OUT1 CMOS polarity
0
Enable SPI control of OUT1 driver control
Select OUT2 Source Control (Register 0x33)
Table 25.
Address 0x33 Bit [7:4] 3 Bit Name Unused OUT2 source Description Unused. Selects the signal source for OUT2. 0 = source for OUT2 is the output of the P1 divider (default). 1 = source for OUT2 is the input reference (REF or XTAL). Unused.
[2:0]
Unused
Rev. C | Page 28 of 32
AD9552
OUT2 Driver Control (Register 0x34)
Table 26.
Address 0x34 Bit 7 Bit Name OUT2 drive strength Description Controls the output drive capability of the OUT2 driver. 0 = weak. 1 = strong (default). Controls power-down functionality of the OUT2 driver. 0 = OUT2 active (default). 1 = OUT2 powered down. OUT2 driver mode selection. 000 = CMOS, both pins active. 001 = CMOS, positive pin active, negative pin tristate. 010 = CMOS, positive pin tristate, negative pin active. 011 = CMOS, both pins tristate. 100 = LVDS. 101 = LVPECL (default). 110 = not used. 111 = not used. Selects the polarity of the OUT2 pins in CMOS mode. 00 = positive pin logic is true = 1, false = 0/negative pin logic is true = 0, false = 1 (default). 01 = positive pin logic is true = 1, false = 0/negative pin logic is true = 1, false = 0. 10 = positive pin logic is true = 0, false = 1/negative pin logic is true = 0, false = 1. 11 = positive pin logic is true = 0, false = 1/negative pin logic is true = 1, false = 0. These bits are ineffective unless Bits[5:3] select CMOS mode. Controls OUT2 driver functionality. 0 = OUT2 is LVDS or LVPECL, per the OUTSEL pin (Pin 15) (default). 1 = OUT2 functionality defined by Bits[7:1].
6
OUT2 power-down
[5:3]
OUT2 mode control
[2:1]
OUT2 CMOS polarity
0
Enable SPI control of OUT2 driver control
Rev. C | Page 29 of 32
AD9552 OUTLINE DIMENSIONS
5.00 BSC SQ 0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ
0.50 BSC
EXPOSED PAD (BOTTOM VIEW)
17 16 8
3.25 3.10 SQ 2.95
0.50 0.40 0.30
9
0.25 MIN 3.50 REF
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 30. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 AD9552BCPZ AD9552BCPZ-REEL7 AD9552/PCBZ
1
Temperature Range -40C to +85C -40C to +85C
Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
011708-A
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
Package Option CP-32-2 CP-32-2
Z = RoHS Compliant Part.
Rev. C | Page 30 of 32
AD9552 NOTES
Rev. C | Page 31 of 32
AD9552 NOTES
(c)2009-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07806-0-7/10(C)
Rev. C | Page 32 of 32

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